Cache memory is a small block of high-speed memory that is typically placed between a data processing unit and a slower main memory. When the processing unit needs to access data stored in the main memory, it first looks to the cache memory to see whether the data is available in the cache. When the processing unit first reads data from the main memory, a copy of that data is stored in the cache as part of a block of information (known as a cache line) that represents consecutive locations of main memory. When the processing unit writes data to the main memory, the data is stored in the cache. When the processing unit subsequently access memory addresses that have been accessed previously or nearby addresses, the processing unit first checks the cache memory rather than the main memory. This approach reduces average memory access time because, when data is accessed at an address in the main memory, later accesses will likely involve data from within the same block (this is the temporal locality principle). The data written into cache memory remains there until certain conditions are met (e.g., the cache memory is full), then a cache line is selected according to a specified criterion (e.g., the one least recently used) and is evicted.
Data caching is typically not done when input/output (I/O) devices write data to main memory because it is unlikely that another transaction will involve the same address as the data previously written by I/O devices. Therefore, a computer chipset that manages data transfers to and from I/O devices typically forwards the write data directly to main memory without caching the data.